Recent advances in computer technology have greatly increased the speed at which computing tasks can be performed. For example, many processing units in computing devices now utilize Chip Multiprocessor (CMP) systems, which allow multiple threads of execution to execute simultaneously on a single chip. A CMP system generally comprises multiple independent processing cores, each of which can share common resources such as Dynamic Random Access Memory (DRAM) for executing respective threads.
However, such a resource sharing scheme poses significant resource managing problems in designing CMP systems. For example, different threads executed by a CMP system can interfere with each other while accessing shared memory resources. Conventional memory access scheduling techniques for CMP systems function by optimizing overall data throughput obtained from the DRAM. However, in doing so, such techniques do not take into account inter-thread interference. As a result, different threads running together on the same chip can experience significantly different memory system performance. For example, one thread can experience a severe slowdown or starvation while another is unfairly prioritized by the memory scheduler. Accordingly, there is a need in the art for memory access scheduling techniques that provide more effective balancing of memory system performance between threads in a CMP system.